Alan Mantooth, in Model-Based Engineering for Complex Electronic Systems, 2013 13.5.5.2 Focusing on Interfaces and Design Complexity Additionally, the architecture of very fast amplifiers usually dictates trade-offs which degrade DC error terms. Fast slewing amplifiers generally have extended ring times, complicating amplifier choice and frequency compensation. There is normally a trade-off between slew and ring time. Ring time defines the region where the amplifier recovers from slewing and ceases movement within some defined error band. During slew time the output amplifier moves at its highest possible speed towards the final value. The delay time is very small and is almost entirely due to propagation delay through the DAC and output amplifier: During this interval there is no output movement. Figure 12.1 shows that DAC settling time has three distinct components. It is usually specified for a full-scale 10V transition.
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DAC settling time is the elapsed time from input code application until the output arrives at and remains within a specified error band around the final value. In particular, the settling time of the DAC and its output amplifier is extraordinarily difficult to determine to 16-bit resolution. AC specifications require more sophisticated approaches to produce reliable information. Measurement techniques are well understood, albeit often tedious. The approach employed permits observation of small amplitude information at the excursion limits of large waveforms without overdriving the oscilloscope.ĭAC DC specifications are relatively easy to verify. This publication's remaining sections describe a method enabling an oscilloscope to accurately display DAC settling time information for a 10V step with 1ppm resolution (10μV) within 265ns. Reliable 1ppm DAC settling time measurement constitutes a high order difficulty problem requiring exceptional care in approach and experimental technique. Dynamic measurement to 20-bit resolution is particularly challenging. Measuring anything at any speed to 20-bit resolution (1ppm) is hard.
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It is expressed as a percentage of full scale or in terms of an LSB value. The differential nonlinearity of a DAC is the maximum deviation from ideal of the analog output between any two adjacent codes. Worst-case settling time is typically measured between the zero-scale and full-scale codes. Usually the output is expected to settle to within an error band of 1 2LSB. The settling time is measured from the instant of a digital-input-code change to the time that the analog output reaches its corresponding new value to within a specified error band. A DAC is generally expected to be monotonic to increments as small as an LSB, but in general the smallest increment for which the DAC remains monotonic determines its monotonicity. Some manufacturers call this parameter the nonlinearity.Ī DAC is said to be monotonic if each digital-code increment produces an output equal to or larger than that of the preceding code. For example, ( 1 2)LSB linearity for an 8-bit DAC corresponds to 0.195%. It is often given as a percentage or as a fraction of an LSB. Linearity is the maximum allowable deviation from an ideal straight line drawn between the zero-scale and full-scale outputs. An 8-bit, DAC has a resolution of 8 bits, or one part in 2 8. The resolution is the smallest increment of output that the DAC can produce.
The resolution of a DAC is given by the number of bits, N. The following is a listing and definitions of key DAC terms and specifications: Digital-to-analog converters are normally chosen for application within a given system on the basis of their resolution and accuracy, which, in turn, is generally determined by N, the number of input bits of the converter.
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